4.6 Article

Bonded planar double-metal-gate NMOS transistors down to 10 nm

Journal

IEEE ELECTRON DEVICE LETTERS
Volume 26, Issue 5, Pages 317-319

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2005.846580

Keywords

double gate; electrical characterization; metal gate; MOS transistors; nano-MOSFETs silicon-on-insulator (S01); wafer bonding

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