Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 52, Issue 9, Pages 2081-2086Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2005.854287
Keywords
CMOS; electromigration (EM); foundry; microelectromechanical devices (MEMS); stress-induced voiding
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Thermal budget limits for low stand-by power (LSP), 0.25 mu m foundry CMOS devices have been investigated, in order to assess the impact of post-processing microelectromechanical devices devices. Resistance increases for vias (metal-to-metal contacts) rather than transistor-performance shifts limits the postprocessing thermal budget. An empirical relation is found to predict the via resistance increase for various annealing conditions, based on third-order reactions of vacancies supplied by surface diffusion of metal atoms. The resistance increase is strongly dependent on annealing time and temperature. With a criterion of 10% increase, 6 h at 425 degrees C, 1 h at 450 degrees C, and 0.5 h at 475 degrees C are the maximum allowable thermal budgets, respectively. Electromigration (EM) of via chain structures was also evaluated, and after annealing for 6 h at 425 'C showed only a 33% decrease in the EM lifetime.
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