On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

According to the recent prediction made by the Semiconductor Industry Association (SIA) in International Technology Roach-nap for Semiconductors (ITRS), the silicon technology will continue its historical rate of advancement with the Moore's law for at least a Couple of decades. With this trend, the silicon gate oxide will be scaled down to its physical limit in order to maintain proper control of the nanosize MOS transistors. This work reviews several critical issues of MOS gate dielectrics in the nanometer range. Although it was suggested that the conventional oxide can be scaled down. in principle. to two atomic layers of about 7 angstrom. this is not practically feasible because of the non-scalabilities of interface. trap capture cross-section. leakage current, and the statistical parameters of fabrication processes. Introducing a high-kappa material can help solving most of the problems by using Physically thicker high-kappa gate dielectric films but several other reliability rises. Being used in the extreme fine structure, the requirements, problems of the MOS device rises for the material properties of the new high-kappa are very stringent. Unfortunately. most of the high-K materials are ionic metal oxides. This fundamental physics results in several undesirable instability issues when interfacing with silicon and with the CMOS processes. Bulk type thin oxynitride/high-kappa stack could be a good solution for the coming technology nodes. (c) 2006 Elsevier B.V. All rights reserved.