Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 41, Issue 12, Pages 2669-2680Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2006.884231
Keywords
analog-to-digital conversion; analog integrated circuits; asynchronous logic circuits; calibration; capacitive ladder; comparators; high-speed integrated circuits; impulse radio; non-binary successive approximation; ultra-wideband (UWB)
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An asynchronous analog-to-digital converter (ADC) based on successive approximation is used to provide a high-speed (600-MS/s) and medium-resolution (6-bit) conversion. A high input bandwidth (> 4 GHz) was achieved which allows its use in RF subsampling applications. By using asynchronous processing techniques, it avoids clocks at higher than the sample rate and speeds up a nonbinary successive approximation algorithm utilizing a series nonbinary capacitive ladder with digital radix calibration. The sample rate of 600 MS/s was achieved by time-interleaving two single ADCs, which were fabricated in a 0.13-mu m standard digital CMOS process. The ADC achieves a peak SNDR of 34 dB, while only consuming an active area of 0.12 mm(2) and having power consumption of 5.3 mW.
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