Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs

In this paper, using three-dimensional statistical numerical simulations, the authors study the intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variations in realistic bulk MOSFETs scaled to 25,18,13, and 9 nm. The scaling is based on a 35 mn MOSFET developed by Toshiba, which has also been used for the calibration of the authors' atomistic device simulator. Special attention is paid to the accurate resolution of the individual discrete dopants in the drift-diffusion simulations by introducing density-gradient quantum corrections for both electrons and holes. In the LER simulations, two scenarios have been aopted: In the first one, LER follows the prescriptions of the International Roadmap for Semiconductors; in the second one, LER is kept constant close to the current best values. Combined effects of the different sources of intrinsic parameter fluctuations have also been simulated in the 35 nm reference devices and the results for the standard deviation of the threshold voltage compared to the measured values.