A CMOS imager with column-level ADC using dynamic column fixed-pattern noise reduction

This paper presents a CMOS imager with column-level ADC that uses a dynamic column fixed-pattern noise (FPN) reduction technique. This technique, called dynamic column switching (DCS), strongly reduces the perceptual effects of nonuniformities introduced by the column-level ADC or any other column-wise circuit element. This relaxes the uniformity requirements on the column-level ADC circuitry, which can significantly decrease power consumption and chip area. The proposed DCS technique requires only five transistors per column and minimal digital overhead at the chip level. A prototype was realized in a 0.18 mu m CMOS process. The implemented column-level ADC uses a single-slope architecture and features a low-power column circuit design. In the measured images, the application of dynamic column switching make a column FPN of +/- 0.67% of full scale nearly invisible to the human eye.