Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 42, Issue 2, Pages 247-257Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2006.889372
Keywords
ADC; analog-to-digital conversion; CMOS; scaleable; successive approximation register; ultra-wideband communication
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Ultra-wideband radio requires Nyquist sampling rates of at least 500 MS/s with low resolutions. While flash is the traditional choice for these specifications, a comparative energy model is used to show the potential energy savings of the time-interleaved successive approximation register architecture, which requires only a linear number of comparisons versus exponential for flash. A dual 500-MS/s, 5-bit ADC chip is implemented in a 0.18-mu m CMOS process, with both ADCs synchronized for use in an I/Q UWB receiver. Each ADC uses a 6-way time-interleaved SAR topology with full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500-MS/s operation with 7.8 mW power consumption. The output resolution is adjustable down to the 1-bit level for additional power savings.
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