Journal
IEEE ELECTRON DEVICE LETTERS
Volume 28, Issue 4, Pages 258-260Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2007.891757
Keywords
CMOS; Fermi-level pinning; HfLaO; high-kappa (HK) dielectric; interfacial dipole; metal gate (MG); work function
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For the first time, we demonstrate experimentally that by using HfLaO high-kappa gate dielectric, the flat-band voltage (V-fb) and the threshold voltage (V-th) of metal-electrode-gated MOS devices can be tuned effectively in a wide range (wider than that from the Si-conduction band edge to the Si-valence band edge) after a 1000-degrees\C annealing required by a conventional CMOS source/drain activation process. As prototype examples shown in this letter, TaN gate with effective work function Phi(m,eff) similar to 3.9-4.2 eV and Pt gate with Phi(m,eff) - 5.5 eV are reported. A specific model based on the interfacial dipole between the metal gate and the HfLaO is proposed to interpret the results. This provides an additionally practical guideline for choosing the appropriate gate stacks and dielectric to meet the requirements of future CMOS devices.
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