Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 42, Issue 4, Pages 739-747Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2007.892169
Keywords
ADC; analog-to-digital conversion; deep-submicron CMOS; successive approximation register; ultra-wideband radio
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A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-mn CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3 and 239 MHz inputs, respectively. The total active area is 0.9 mm(2), and the ADC consumes 6 mW from a 1.2-V supply.
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