Journal
APPLIED PHYSICS LETTERS
Volume 90, Issue 14, Pages -Publisher
AMER INST PHYSICS
DOI: 10.1063/1.2720640
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One of the fundamental limits in the scaling of metal oxide semiconductor field-effect transistor technology is the room-temperature (RT) limit of similar to 60 mV/decade in the inverse subthreshold slope. Here, the authors demonstrate vertical integration of a single surround-gated silicon nanowire field-effect transistor with an inverse subthreshold slope as low as 6 mV/decade at RT that spans four orders of magnitude in current. Operation of the device is based on avalanche breakdown in a partially gated vertical nanowire, epitaxially grown using the vapor-liquid-solid method. Low-power logic based on impact ionization field-effect transistors in combination with a vertical architecture is very promising for future high-performance ultrahigh-density circuits. (c) 2007 American Institute of Physics.
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