Journal
IEEE ELECTRON DEVICE LETTERS
Volume 28, Issue 5, Pages 449-451Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2007.895445
Keywords
Flash; memory; nanocrystal; pillar; retention; sidewall; vertical
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We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F(2)), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar Flash memory arrays. Discrete SiGe nanocrystals that are grown by conformal chemical vapor deposition process on the pillar sidewalls form the floating gate and render excellent retention properties at room temperature and at 85 degrees C. The cell shows a large memory window of similar to 1 V and endurance of more than 10(5) cycles.
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