Latency and power measurements on a 64-kb hybrid Josephson-CMOS memory

A 64-kbit sub-nanosecond Josephson-CMOS hybrid RAM memory is being developed with hybrid high-speed interface circuits. The hybrid memory is designed and fabricated using a commercially available 0.18 mu m CMOS process and NEC-SRL's 2.5 kA/cm(2) Nb process for Josephson junctions. The memory bit-line output signals are detected by ultra-low power, high-speed Josephson devices. The most challenging part of the memory system is the input amplifier; the performance of this amplifier is optimized by minimizing its parasitic capacitance loading. Functionality tests were reported at the ASC 2004, high-speed measurements are the focus of this paper. Most of the power dissipation,in the memory system occurs in the input interface circuits. The power dissipation and delay for the interface circuit are reported. The delay time and power dissipation of the CMOS part (including drivers, decoders, and cells), which contributes most to the total access time of the hybrid memory, are measured. The relation of measurements to simulations will be presented. Plans for future designs to reduce power dissipation and latency are described.