Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 54, Issue 7, Pages 1784-1788Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2007.899401
Keywords
CMOS; drain-induced barrier lowering (DIBL); quasi-SOI; scaling; short-channel effects (SCEs); SOI; ultrathin; body (UTB)
Ask authors/readers for more resources
Results from a novel quasi-SOI CMOS architecture fabricated on bulk Si are reported for the first time, demonstrating its viability as an alternative device for the nanometer regime. All of the processing is basically compatible with the conventional CMOS technology. The short-channel effects and the drain-induced barrier-lowering effects can be effectively suppressed by the L-type insulator surrounding the source/drain regions. In addition, quasi-SOI MOSFETs can be more tolerant of process-induced variation for the deep nanometer regime. The quasi-SOI MOSFET can be considered as one of the promising candidates for highly scaled devices.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available