4.6 Article

A model for electromigration-induced degradation mechanisms in dual-inlaid copper interconnects: Effect of microstructure

Journal

JOURNAL OF APPLIED PHYSICS
Volume 102, Issue 5, Pages -

Publisher

AMER INST PHYSICS
DOI: 10.1063/1.2775538

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A developed physical model and a simulation algorithm are used to predict electromigration (EM)-induced stress evolution in dual-inlaid copper interconnects. Incorporation of all important atom migration driving forces into the mass balance equation and its solution, together with the solution of the coupled electromagnetics and elasticity problems, allows the simulation of EM-induced degradation in a variety of dual-inlaid copper interconnect segments with different dominant paths for mass transport [V. Sukharev and E. Zschech, J. Appl. Phys. 96, 6337 (2004)]. The results of the numerical simulation have been proven experimentally by EM degradation studies on fully embedded dual-inlaid copper interconnect test structures and by subsequent microstructure analysis, mainly based on electron backscatter diffraction (EBSD) data. The EM-induced void formation and its virtual movement and growth in a copper interconnect were continuously monitored in an in situ scanning electron microscopy experiment. The copper microstructure, particularly the orientation of grains and grain boundaries, was determined with EBSD. It has a significant influence on grain boundary diffusivity and consequently on the mass transport along grain boundaries. For interconnects with interfaces that resist atomic transport and where grain boundaries are the important pathways for atom migration [E. Zschech , Z. Metallkd. 96, 996 (2005)], degradation and failure processes are completely different for microstructures with randomly oriented grain boundaries compared with bamboolike microstructures. The correspondence between simulation results and experimental data indicates the applicability of the developed model for optimization of the physical and electrical design rules. Simulation-based optimization of the interconnect architecture, segment geometry, material properties, and some of the process parameters can produce on-chip interconnect systems with a high immunity to EM-induced failures. (C) 2007 American Institute of Physics.

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