Journal
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume 72, Issue 1, Pages 289-292Publisher
SPRINGER
DOI: 10.1007/s10470-012-9865-0
Keywords
Analog circuits; Tunable circuits; CMOS transconductors
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A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master-slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 mu m CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 mu A current consumption.
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