Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS

We report on the design and characterization of an ultralow-power converter, designed for use in baseband digitization in wireless sensor network radio receivers. The converter uses a successive approximation architecture and operates robustly with a supply voltage as low as 450 mV, overcoming charge leakage limitations. Implemented in a 90 mn CMOS process, this design achieves a figure of merit of 0.14 pJ/Conv.Step for the converter core and shows the integration of a complete data-conversion subsystem, including reference generation, from a 0.5 V supply.