Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 42, Issue 11, Pages 2348-2356Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2007.906210
Keywords
analog-to-digital conversion; charge leakage; CMOS; digital calibration; low power; low voltage; subthreshold; successive approximation
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We report on the design and characterization of an ultralow-power converter, designed for use in baseband digitization in wireless sensor network radio receivers. The converter uses a successive approximation architecture and operates robustly with a supply voltage as low as 450 mV, overcoming charge leakage limitations. Implemented in a 90 mn CMOS process, this design achieves a figure of merit of 0.14 pJ/Conv.Step for the converter core and shows the integration of a complete data-conversion subsystem, including reference generation, from a 0.5 V supply.
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