Journal
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Volume 44, Issue 6, Pages 1263-1276Publisher
WILEY
DOI: 10.1002/cta.2160
Keywords
chaos; multi-scroll; chaotic attractor; delay; delay line; priority encoder; FPGA
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In this paper, the first generalization for time-delay sampled-data chaotic system in order to generate multi-scroll attractor is introduced with its circuit implementation. An efficient delay-line with binary priority encoding, parallel shifting, and binary decoding is also suggested and implemented to overcome the delay line realization drawback in such systems. The proposed system enhances the complexity of chaotic behavior by means of multi-scroll feature and exemplifies the simplification of chaotic systems for better realizations. Copyright (c) 2015 John Wiley & Sons, Ltd.
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