Fault tolerant adaptive write schemes for improving endurance and reliability of memristor memories

The non-deterministic nature of memristor and its unreliable behavior are the two major concerns hampering its growth and industrial manufacturability. The endurance and reliability of memristor memories are affected not only by the process variations (intrinsic), but also due to the electrical stress created by interfacing peripheral circuits (extrinsic). Concerning the intrinsic faults in transition metal oxide (TMO) memristors, drifting of oxygen vacancies across the device is responsible for SET/RESET operation. It is likely that such drifting might induce switching faults during the device operation, for instance endurance of the memory. Thus, the application of a fixed write pulse may not suffice to achieve successful write operations under these circumstances. To circumvent the above pitfall, we propose here a new technique by designing a fault tolerant adaptable write scheme which can adapt by itself based on the behavior and switching faults. Accordingly, the proposed write scheme identifies the optimal amplitude and the width for write pulse. The proposed write scheme under various memristor faults is found to enhancing the reliability of memristors efficiently. Further, the results are validated by means of Monte-Carlo analysis by infusing the random variations of internal parameters of memristors as well.