Low-Power Soft Error Hardened Latch

This paper presents a low-power soft-error hardened pulsed latch suitable for reliable circuit operation. The proposed circuit is aimed to tackle the particle hit effect on the internal nodes and on the external logic, simultaneously. The hardening method is based on redundant feedback loop to protect internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from combinational logic. The proposed circuit has less timing overhead and negative setup time. The HSPICE post-layout simulation in 90 nm CMOS technology reveals that circuit is able to recover from almost any single particle strike on internal nodes and tolerates input transients up to 130 ps of duration.