Journal
JOURNAL OF SEMICONDUCTORS
Volume 31, Issue 10, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.1088/1674-4926/31/10/104009
Keywords
multi-bit storage; non-uniform channel; charge trapping memory; NAND array; SiON layer
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Funding
- National Basic Research Program of China [2006CB302700]
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In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory (NUC-CTM) device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect (SBE) and provide 3-bit per cell capability. Owing to the n_ buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.
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