4.8 Article

Tunable Charge-Trap Memory Based on Few-Layer MoS2

Journal

ACS NANO
Volume 9, Issue 1, Pages 612-619

Publisher

AMER CHEMICAL SOC
DOI: 10.1021/nn5059419

Keywords

charge-trap memory; MoS2; memory window; dual gate; memory characteristics

Funding

  1. National Young 1000 Talent Plan
  2. Pujiang Talent Plan in Shanghai
  3. National Natural Science Foundation of China [61322407, 11474058]
  4. Chinese National Science Fund for Talent Training in Basic Science [J1103204]

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Charge-trap memory with high-kappa dielectric materials is considered to be a promising candidate for next-generation memory devices. Ultrathin layered two-dimensional (2D) materials like graphene and MoS2 have been receiving much attention because of their fantastic physical properties and potential applications in electronic devices. Here, we report on a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. Because of the extraordinary trapping ability of both electrons and holes in HfO2, the MoS2 memory device exhibits an unprecedented memory window exceeding 20 V. Importantly, with a back gate the window size can be effectively tuned from 15.6 to 21 V; the program/erase current ratio can reach up to 10(4), allowing for multibit information storage. Moreover, the device shows a high endurance of hundreds of cycles and a stable retention of similar to 28% charge loss after 10 years, which is drastically lower than ever reported MoS2 flash memory. The combination of 2D materials with traditional high-kappa charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.

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