Journal
ACS NANO
Volume 8, Issue 4, Pages 4023-4032Publisher
AMER CHEMICAL SOC
DOI: 10.1021/nn501181t
Keywords
2D layers; MoS2; transistor; memory; plasma etching; charge trapping
Categories
Funding
- NSF [ECCS-1307744, DMR-0320740, 0315633, ECCS-0922972]
- Direct For Mathematical & Physical Scien
- Division Of Materials Research [0315633] Funding Source: National Science Foundation
- Directorate For Engineering [1307744] Funding Source: National Science Foundation
- Div Of Electrical, Commun & Cyber Sys [1307744] Funding Source: National Science Foundation
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New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials In nanoelectronic applications.
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