3.9 Article Proceedings Paper

Efficient Virtualization on Embedded Power Architecture® Platforms

Journal

ACM SIGPLAN NOTICES
Volume 48, Issue 4, Pages 445-457

Publisher

ASSOC COMPUTING MACHINERY
DOI: 10.1145/2499368.2451163

Keywords

Performance; Design; Virtualization; Virtual Machine Monitor; Dynamic Binary Translation; Power Architecture Platforms; Architecture Design; Code Patching; TLB; In-place Binary Translation; Read/write Tracing; Adaptive Page Resizing; Adaptive Data Mirroring

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Power Architecture (R) processors are popular and widespread on embedded systems, and such platforms are increasingly being used to run virtual machines [11, 22]. While the Power Architecture meets the Popek-and-Goldberg virtualization requirements for traditional trap-and-emulate style virtualization, the performance overhead of virtualization remains high. For example, workloads exhibiting a large amount of kernel activity typically show 3-5x slowdowns over bare-metal. Recent additions to the Linux kernel contain guest and host side paravirtual extensions for Power Architecture platforms. While these extensions improve performance significantly, they are guest-specific, guest-intrusive, and cover only a subset of all possible virtualization optimizations. We present a set of host-side optimizations that achieve comparable performance to the aforementioned paravirtual extensions, on an unmodified guest. Our optimizations are based on adaptive in-place binary translation. Unlike the paravirtual approach, our solution is guest neutral. We implement our ideas in a prototype based on Qemu/KVM. After our modifications, KVM can boot an unmodified Linux guest around 2.5x faster. We contrast our optimization approach with previous similar binary translation based approaches for the x86 architecture [4]; in our experience, each architecture presents a unique set of challenges and optimization opportunities.

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