Journal
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS
Volume 4, Issue 4, Pages -Publisher
ASSOC COMPUTING MACHINERY
DOI: 10.1145/1412587.1412593
Keywords
3D integration; stacking process; design; hardware
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We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7 Omega between a through-silicon via (TSV) and a microbump. We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 0.18um CMOS technology based on 8-inch wafers. The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption. The yields obtained from the results comprising all functional tests are over 60%.
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