Journal
IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 30, Issue 10, Pages 5425-5438Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2014.2377152
Keywords
Common-mode voltage (CMV); multilevel inverter; pulse width modulation (PWM); switching loss
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Funding
- Vietnam National Foundation for Science and Technology Development (NAFOSTED) [103.01-2011.67]
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This paper introduces a novel pulse width modulation (PWM) technique to eliminate common-mode voltage in odd-multilevel inverters using the three zero common-mode vectors principles. Similarly, as in conventional PWM for multilevel inverters, this PWM can be properly depicted in an active two-level voltage inverter. With the help of two standardized PWM patterns, the characteristics of the PWM process can be fully explored in that active inverter as a switching time diagram and switching state sequence. Due to an unequal number of commutations of three phases in each sampling period, the switching loss is optimized by a proposed current-based mapping algorithm. The switching loss reduction can be up to 25% compared to the same PWM technique with nonoptimized algorithms. The PWM method has been then generalized as an equipotential PWM control, which is valid to both odd-and even-multilevel inverters. The theoretical analysis is verified by simulation and experimental results.
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