Journal
IEEE TRANSACTIONS ON POWER ELECTRONICS
Volume 30, Issue 12, Pages 6817-6828Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TPEL.2015.2389151
Keywords
Dynamic dead-time controller (DDTC); high-frequency boost converters; high-voltage (HV) synchronous gate driver; quasi-square-wave zero-voltage switching (QSW-ZVS); zero-voltage switching (ZVS) technique
Categories
Funding
- ARPA-E ADEPT Program [DE-AR0000105]
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This paper presents techniques to enable non-isolated boost converters to achieve high power efficiencies under high switching frequency and high-voltage conditions. A quasi-square-wave zero-voltage switching (QSW-ZVS) boost converter topology is proposed to achieve high-frequency soft switching without any coupled inductors in the power stage and, thus, minimize the switching power loss of the converter. An on-chip dynamic dead-time controller is developed to provide near-optimum dead time for power FETs during switching transitions under different output voltage and load current conditions in order to achieve ZVS with minimal body diode conduction loss of power FETs. Asynchronous gate driver is also proposed to provide fast propagation delays and output signal rise/fall time, enabling megahertz operation of the converter. A hardware boost converter prototype is built with the synchronous gate driver circuitry implemented in a 0.5-mu m high-voltage CMOS process. The proposed QSW-ZVS boost converter provides an output voltage of 150 V and delivers an output power of 130 W. The peak power efficiency of the proposed converter achieves 92.7% at the switching frequency of 1 MHz. Compared with state-of-the-art gate drivers, the worst-case propagation delay of the proposed synchronous gate driver is improved by at least 7.6 times. The operation frequency of the proposed non-isolated boost converter is also improved by at least 15 times compared with other state-of-the-art counterparts.
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