Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 62, Issue 11, Pages 3633-3639Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2015.2475604
Keywords
III-V; border trap; characterization; InGaAs; mobility; quantum well; reliability
Funding
- Engineering and Physical Sciences Research Council [EP/L010607/1] Funding Source: researchfish
- EPSRC [EP/L010607/1] Funding Source: UKRI
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Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection.
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