Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 62, Issue 5, Pages 1491-1497Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2015.2414711
Keywords
Flash memories; program/erase (P/E) cycling; semiconductor device modeling; semiconductor device reliability
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This paper presents an in-depth comparative analysis of the major physical constraints to the width of the threshold-voltage distribution of a state-of-the-art NAND Flash array. The analysis addresses both time-0 placement by program-and-verify algorithms on fresh and cycled arrays and distribution widening during idle/bake periods. Results allow to identify how each physical effect impacts the threshold-voltage distribution as a function of array program conditions, temperature, cycling, and duration of idle/bake periods, providing clear hints for the design of next generation technology nodes.
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