Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 62, Issue 2, Pages 478-484Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2014.2381560
Keywords
2-D modeling; OFF-state current; ON-state current; silicon on insulator (SOI); subthreshold slope (SS); tunneling field-effect transistor (TFET)
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In this paper, we have developed a compact analytical model for the drain current of a silicon-on-insulator tunneling field-effect transistor. The model includes the effects of oxide thickness, body doping, drain voltage, and gate metal work function. The model calculates the drain current using a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against 2-D numerical simulations. The model predicts the drain current accurately in both the ON state (strong inversion) as well as in the subthreshold region.
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