Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 62, Issue 6, Pages 1870-1878Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2015.2420690
Keywords
AlGaN/GaN; capacitance-voltage (C-V); frequency/temperature dispersion; interface traps; metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs); pulse-mode current-voltage; threshold voltage instability
Funding
- National Natural Science Foundation of China/Research Grants Council Joint Research Scheme [N_HKUST636/13]
- Innovation and Technology Fund [ITS/192/14FP]
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Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth.
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