Journal
OPTICAL MICROLITHOGRAPHY XXV, PTS 1AND 2
Volume 8326, Issue -, Pages -Publisher
SPIE-INT SOC OPTICAL ENGINEERING
DOI: 10.1117/12.920053
Keywords
NAND; DRAM; patterning; EUV; double patterning; multiple patterning
Categories
Ask authors/readers for more resources
Memory devices such as DRAM and NAND flash will continue to increase their capacity through scaling, which will extend to below the 10nm regime. From a device physics perspective, there are possible solutions for scaling below 10nm. However, the challenges of sub-10nm scaling will come from the productivity. In fact, major challenges for the realization of high density memory devices are lithography and vertical etching of high aspect ratio holes in DRAM and 3D flash memories. Here, status and the direction of DRAM and flash memory scaling technologies will be reviewed with a special focus on the extendibility from not only device physics but also productivity points of view.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available