A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA

When conventional biasing topologies are employed, near sub-threshold operated amplifiers show large performance deviations under unavoidable PVT variations. Moreover, these effects become severe when these circuits are implemented in subnanometer technologies. This paper introduces a new type of compensation technique to realize a reliable low voltage, low-noise amplifier that is achieved by stabilizing the core device trans-conductance (g(m)). To minimize the g(m) variation, the proposed technique uses an error voltage generated by comparing the LNA current with a stable constant current reference (CCR). Not only the compensation circuits, a new low-voltage self-biased CCR source is also introduced which is based on conventional beta multiplier that can operate with a voltage as low as 0.4 V with a resulting TC (temperature coefficient) of 118 ppm/degrees C for typical-typical corner case. The g(m) and S-21 of the compensated 65 nm LNA core device shows 8 x times lower variations compared to that of a conventional one when temperature varies from -20 to 110 degrees C and with the consideration of five process corner cases. Finally, Monte Carlo estimation for both process and mismatch shows 34% reduction in standard deviation of S-21 and 20% improvement in yield compared to a conventionally biased LNA. The compensated LNA with all its accessories consumes 402 mu W power when operated at a supply voltage of 0.6 V.