Journal
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
Volume 25, Issue 3, Pages -Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TASC.2014.2377744
Keywords
Josephson devices; Josephson junctions; Josephson logic; superconducting device fabrication; superconducting integrated circuits; superconductor-normal-superconductor devices
Funding
- National Institute of Standards and Technology
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Analysis of the Josephson junction yield in the National Institute of Standards and Technology 10 V Programmable Josephson Voltage Standard (PJVS) has been performed by fabricating and measuring over 25 million Nb/NbxSi1-x/Nb junctions. Using the 265 116 junctions per PJVS device, it was possible to measure Shapiro steps on current voltage curves and then estimate the number of single-junction defects within these long arrays. By comparing the results of a quantum-based measurement to a model simulating junction defects, the quantity and magnitude of a small number of junction defects can be estimated from an array of many thousands of junctions. Understanding the source of junction defects in the fabrication process is important for maximizing yield and uniformity, both of which directly relate to the current margin of the quantized voltage step. We have recently fabricated 18 imperfect but usable PJVS devices and 16 that were free from defects, many with n = 1 Shapiro step margins approximately equal to 2 mA. The best of these wafers had a junction defect density of around 3 in a million.
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