Performance of a 650V SiC diode with reduced chip thickness

A significant performance gain of 650V SiC diodes is possible by reducing the wafer thickness from the standard thickness of 350 mu m to < 150 mu m. Not only the differential resistance of the diodes but also the R-th benefit from this chip thickness reduction. As consequence a further chip size reduction with accompanying capacitive charge reduction leads to a device with improved efficiency in PFC applications under both high load and low load conditions.