Journal
IEEE MICRO
Volume 35, Issue 3, Pages 58-70Publisher
IEEE COMPUTER SOC
DOI: 10.1109/MM.2015.50
Keywords
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Funding
- CFAR, one of six centers of STARnet, a Semiconductor Research Corporation program - MARCO
- DARPA [HR0011-13-C-0022]
- National Science Foundation (NSF) Expeditions in Computing Award [CCF-0926148]
- Google Faculty Research Award
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THE AUTHORS DEVELOPED ALADDIN, A PRE-RTL, POWER-PERFORMANCE ACCELERATOR MODELING FRAMEWORK AND DEMONSTRATED ITS APPLICATION TO SYSTEM-ON-CHIP (SOC) SIMULATION. ALADDIN ESTIMATES PERFORMANCE, POWER, AND AREA OF ACCELERATORS WITHIN 0.9, 4.9, AND 6.6 PERCENT WITH RESPECT TO REGISTER-TRANSFER LEVEL (RTL) IMPLEMENTATIONS. INTEGRATED WITH ARCHITECTURE-LEVEL GENERAL-PURPOSE CORE AND MEMORY HIERARCHY SIMULATORS, ALADDIN PROVIDES A FAST BUT ACCURATE WAY TO MODEL ACCELERATORS' POWER AND PERFORMANCE IN AN SOC ENVIRONMENT.
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