4.6 Article

Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories

Journal

IEEE ELECTRON DEVICE LETTERS
Volume 36, Issue 11, Pages 1157-1159

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2015.2481819

Keywords

RRAM; multilevel; programming scheme

Funding

  1. [NSF-CCF-1449653]

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Analog weight tuning in resistive memories is attractive for multilevel operation and neuro-inspired computing. To tune the device conductance to the desired states as fast as possible without sacrificing the accuracy, we propose an optimization programming protocol by adjusting the pulse amplitude incremental steps, the pulsewidth incremental steps, and the start voltages. Our experimental results on HfOx-based resistive memories indicate that avoiding over-reset by appropriate programming parameters is critical for fast convergence of the conductance tuning. The over-reset behavior is caused by the stochastic nature of filament formation and rupture, as simulated by a 1-D filament model.

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