Journal
ADVANCED SEMICONDUCTOR-ON-INSULATOR TECHNOLOGY AND RELATED PHYSICS 16
Volume 53, Issue 5, Pages 105-114Publisher
ELECTROCHEMICAL SOC INC
DOI: 10.1149/05305.0105ecst
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In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The fabricated MGN-WFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure.
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