Journal
JOURNAL OF PHYSICS-CONDENSED MATTER
Volume 30, Issue 26, Pages -Publisher
IOP PUBLISHING LTD
DOI: 10.1088/1361-648X/aac5b4
Keywords
TFET; tunneling; nanowires; III-V; heterostructures; subthreshold slope
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Funding
- EU via FP7 project E2SWITCH [619509]
- European Project STEEPER [257267]
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The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III-V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.
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