Atomistic modeling trap-assisted tunneling in hole tunnel field effect transistors

Tunnel Field Effect Transistors (FETs) have the potential to achieve steep Subthreshold Swing (S.S.) below 60 mV/dec, but their S.S. could be limited by trap-assisted tunneling (TAT) due to interface traps. In this paper, the effect of trap energy and location on OFF-current (IOFF) of tunnel FETs is evaluated systematically using an atomistic trap level representation in a full quantum transport simulation. Trap energy levels close to band edges cause the highest leakage. Wave function penetration into the surrounding oxide increases the TAT current. To estimate the effects of multiple traps, we assume that the traps themselves do not interact with each other and as a whole do not modify the electrostatic potential dramatically. Within that model limitation, this numerical metrology study points to the critical importance of TAT in the IOFF in tunnel FETs. The model shows that for Dit higher than 10(12) / (cm(2) eV) I-OFF is critically increased with a degraded I-ON / I-OFF ratio of the tunnel FET. In order to have an I-ON / I-OFF ratio higher than 10 4, the acceptable Dit near Ev should be controlled to no larger than 10(12) / (cm(2) eV) . Published by AIP Publishing.