4.2 Article

Performance Evaluation of Digital Comparator Using Different Logic Styles

Journal

IETE JOURNAL OF RESEARCH
Volume 64, Issue 3, Pages 422-429

Publisher

TAYLOR & FRANCIS LTD
DOI: 10.1080/03772063.2017.1323564

Keywords

Digital comparator; Half adder logic technique; Power dissipation; Propagation delay; Transmission gate logic technique; Transistor count

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In the present scenario, low power, speed, and size play a significant role specifically in the field of digital VLSI circuits. The major goal of this paper is to design and implement a digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. The results of this paper are simulated on the EDA tanner tool realized in 45-nanometer technology at 0.7 v supply voltage.

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