Journal
IET CIRCUITS DEVICES & SYSTEMS
Volume 12, Issue 1, Pages 17-24Publisher
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-cds.2016.0342
Keywords
time-digital conversion; clocks; delay lines; delay lock loops; charge pump circuits; timing jitter; CMOS integrated circuits; mean square error methods; delay-locked loop; low-jitter DLL; high-resolution time-to-digital converter; two-segment TDC; low-jitter outputs; uniformly distributed multiphase clocks; voltage-controlled delay line; VCDL; static phase offset; locked state; charge pump; interior feedback loop; current matching; discharging currents; phase detector; linearity property; noise suppression; clock jitter; TSMC complementary metal-oxide-semiconductor process; root mean square; clock period counting; eight-phase discrimination; size 0; 35 mum; frequency 60 MHz to 240 MHz; time 3; 6 ps; time 35; 07 ps
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Funding
- National Key Research and Development Program of China [2016YFB0400904]
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A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 mu m complementary metal-oxide-semiconductor process, the measurement results show that DLL's frequency locking range is 60-240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <1 ns and maximum range of around 1 mu s as well as the differential non-linearity <0.68 LSB and the integration non-linearity within -0.97 to 1.24 LSB are obtained for two-segment TDC.
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