Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 26, Issue 12, Pages 2661-2670Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2018.2823274
Keywords
Current starved ring oscillator (CSRO); hardware security; jitter; nonvolatile memory; random telegraph noise (RTN); resistive RAM (RRAM); true random number generator (TRNG)
Funding
- National Science Foundation [CNS-1722557, CCF-1718474, DGE-1723687]
- DARPA Young Faculty Award [D15AP00089]
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In this paper, we propose a high-speed (kilohertz-megahertz), reconfigurable current starved ring oscillator (CSRO)-based true random number generator (TRNG) design. The proposed TRNG exploits the intradevice stochastic variations in resistive RAM switching parameters and random telegraph noise (RTN). We demonstrate the effect of RTN on the jitter of CSRO oscillations. We also propose a methodology to reconfigure the TRNG to generate new random numbers. The proposed 10-bit TRNG is validated by NIST test suite for randomness in the data stream. Energy/bit is 22.8 fJ for generation, and the speed of random data generation is 6 MHz. Security vulnerabilities and countermeasures of the proposed TRNG are also investigated.
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