Journal
IEEE TRANSACTIONS ON SOFTWARE ENGINEERING
Volume 45, Issue 12, Pages 1270-1291Publisher
IEEE COMPUTER SOC
DOI: 10.1109/TSE.2018.2837759
Keywords
Simulated annealing; Graphics processing units; Parallel processing; Benchmark testing; Upper bound; Scalability; Covering arrays; parallel computing; graphics processing units; CUDA; metaheuristic search; constraint satisfaction problem
Funding
- Scientific and Technological Research Council of Turkey [113E546]
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We present a configurable, hybrid, and parallel covering array constructor, called CHiP. CHiP is parallel in that it utilizes vast amount of parallelism provided by graphics processing units (GPUs). CHiP is hybrid in that it bundles the bests of two construction approaches for computing covering arrays; a metaheuristic search-based approach for efficiently covering a large portion of the required combinations and a constraint satisfaction-based approach for effectively covering the remaining hard-to-cover-by-chance combinations. CHiP is configurable in that a trade-off between covering array sizes and construction times can be made. We have conducted a series of experiments, in which we compared the efficiency and effectiveness of CHiP to those of a number of existing constructors by using both full factorial designs and well-known benchmarks. In these experiments, we report new upper bounds on covering array sizes, demonstrating the effectiveness of CHiP, and the first results for a higher coverage strength, demonstrating the scalability of CHiP.
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