Planar Transformers With Near-Zero Common-Mode Noise for Flyback and Forward Converters

Flyback and forward converters are two commonly used topologies for isolated low-power applications. These converters are simple and cost effective and provide galvanic isolation, which make them desirable for low-power levels. In order to enhance the performance of these converters, planar transformers (PTs) can be used that feature lower height, considerably lower leakage inductance, excellent thermal characteristics, and repeatability. Selecting a proper winding arrangement for a PT is a significant challenge, in particular given the large capacitances involved in flat structures. While interleaved structures significantly reduce the ac resistance and leakage inductance of PTs, they also lead to very large interwinding capacitance, which produces significant levels of undesired common-mode (CM) noise that causes EMI problems. Reducing interwinding capacitance by using noninterleaved structures is not an ideal solution to the CM noise problem because of its side effects. Instead, this paper tackles the problem by proposing the concept of paired layers. According to this concept, there are layers in the primary and secondary sides that have the same dv/dt, and therefore, their overlapping does not generate CM noise. These layers can be used to design highly interleaved structures that not only have very low ac resistance and leakage inductance, but also generate almost zero CM noise, although they may have a very large interwinding capacitance. In addition, a detailed parasitic capacitance model of PTs is proposed, which analytically validates the proposed concept and method. The experimental results show that the proposed PTs not only have very low ac resistance and leakage inductance, but also generate extremely low levels of CM noise. Considering that the proposed PT has interwinding capacitance equal to 700 pF, it is very interesting to see that it generates significantly less CM noise than does a traditional wire-wound transformer that has only 10-pF parasitic capacitance. Therefore, the proposed method gives designers the opportunity to minimize ac resistance and leakage inductance by using highly interleaved structures, without having to worry about CM noise caused by large interwinding capacitance.