Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 65, Issue 6, Pages 2439-2445Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2018.2824985
Keywords
Enhancement mode (E-mode); GaN nanowire (NW); logic circuit; MOSFET; switching; top-down; vertical transistor
Funding
- German Research Foundation (DFG)
- Lower Saxony Ministry for Science and Culture (N-MWK)
- China Scholarship Council [201206010284]
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This paper reports on the normally off GaN vertical MOSFETs based on nanowires (NWs) with an inverted p-GaN channel and a wrap-around-gate structure for the first time. Both inductively coupled plasma dry reactive-ion etching and wet-chemical etching were employed to fabricate the vertically aligned GaN NWs from epitaxial thin filmswith a specifieddopingprofile. During the wet etching, the influence of p-doping on the NW morphology was investigated, and the results could be explained by the proposed model. In comparison with other c-axis NW transistors, an enhancement-mode (E-mode) operation with a superior threshold voltage (V-th) of 2.5 V has been reached in the fabricated GaN MOSFETs. Furthermore, a high driving-current density of 101 kA/cm(2) as well as a high ON-/OFF-current ratio of 10(9) was obtained in the NWs, predicting a potential approach toward future GaN electronics with vertical and smart architecture.
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