Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 65, Issue 6, Pages 2461-2469Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2018.2829122
Keywords
Charge trapping; ferroelectric FET (FeFET); Hf0.5Zr0.5O2 (HZO); interlayer (IL)
Funding
- Global Research Corporation
- Semiconductor Research Corporation
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We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify VTH shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and VTH shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 degrees C and endurance up to 5 x 10(6) cycles initiated by the IL breakdown. Endurance up to 10(12) cycles of partial polarization switching is shown inmetal-FE-metal capacitor, in the absence of IL. A comprehensive metal-FE-insulator-semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.
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