4.6 Article

Dynamic Capacitance Model of a Pinned Photodiode in CMOS Image Sensors

Journal

IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 65, Issue 7, Pages 2892-2898

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2018.2831719

Keywords

CMOS image sensor (CIS); full-well capacity (FWC); photodiode capacitance; pinned photodiode (PPD); temperature

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The charge holding capacity of a pinned photodiode (PPD) in CMOS image sensors (CISs) is determined by the capacitance of the photodiode. A PPD with a higher full-well capacity (FWC) is desirable for a higher dynamic range and image contrast thereby improving the image quality. The dependence of FWC of a PPD on light intensity and integration time is reported in the literature. However, there is no generalized method to estimate the PPD capacitance. The reported models assume the PPD capacitance to be constant and independent of operating conditions. This paper presents an improved model to accurately estimate the dynamic behavior of the PPD capacitance at low and high light intensity levels and varying temperature in CISs. It is observed that the logarithmic increase in light intensity and integration time increases the photodiode capacitance linearly. The model shows good agreement with the simulated and measured values of photodiode capacitance.

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