Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 65, Issue 12, Pages 1904-1908Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2018.2822811
Keywords
Design methodology; successive approximation register (SAR) ADC; capacitor-DAC (CDAC) compiler; analog circuit synthesis; skewed NAND-based comparator; synthesizable bootstrapped switch; standard cell
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Funding
- Samsung Research Funding Center of Samsung Electronics [SRFC-IT1502-04]
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This brief proposes a code-reusable design methodology for synthesizable successive approximation register (SAR) ADCs based on the digital design flow to significantly reduce design effort. The SAR ADCs are composed of a capacitor-DAC (CDAC) macro cell generated by a CDAC compiler and analog functional blocks implemented utilizing digital standard cells. Two prototypes of SAR ADCs (12-bit 100 kS/s and 11-bit 50 MS/s) are fabricated in different CMOS processes (180 nm and 28 nm). The prototype ADCs prove the effectiveness of the proposed design methodology with comparable performances with full-custom designed SAR ADCs.
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