A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silicon measurement results verify the validity of this topology. Integration of the proposed readout circuit with the MRAM bitcells is discussed. Measurement results show an integrated input noise of 89 mu Vrms, and reliable sensing of signal level of 1 mV.