Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 53, Issue 3, Pages 896-905Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2786724
Keywords
Current reuse; inverter-stacking amplifier; noise efficiency factor (NEF); power efficient; replica-based bias
Categories
Funding
- NSF [1254459, 1509767, 1527320]
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [1254459] Funding Source: National Science Foundation
- Div Of Electrical, Commun & Cyber Sys
- Directorate For Engineering [1509767] Funding Source: National Science Foundation
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This paper presents a highly power-efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves six-time current reuse, thereby significantly boosting the transconductance and lowering noise but without increasing the current consumption. A novel biasing scheme is devised to ensure robust operation under 1-V supply. A prototype in 180-nm CMOS has 5.5-mu V-rms noise within 10-kHz BW while consuming only 0.25-mu W power, leading to a noise efficiency factor of 1.07, which is the best among reported amplifiers.
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